| Type
|
Platform
|
Description
|
| Platform for Digital ASIC
|
0.5µm
|
0.5µm logic process /usable gates: 500k gates / frequency: 50MHz /supply voltage: 5V
TID>100KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU LETTH >37 MeV·cm2·mg-1
|
| 0.18µm
|
0.18µm logic process / usable gates: 5 million gates / frequency: 200MHz /supply voltage: 1.8/3.3V
TID>100KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU LETTH >15 MeV·cm2·mg-1
|
| 65nm
|
65nm low leakage logic process / usable gates: 50 million gates / frequency: 500MHz /supply voltage: 1.2/3.3V
TID>300KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU Rate<10-10 error/bit-day
|
| 28nm
|
28nm logic process / usable gates: 200 million gates / frequency: 800MHz /supply voltage: 1.05/1.8/3.3V
TID>300KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU Rate<10-10 error/bit-day
|
| Analog IP
|
0.5µm
|
IP: PSOS/SRAM
TID>100KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU LETTH >37 MeV·cm2·mg-1
|
| 0.18µm
|
IP: PLL/LVDS/LVPECL/PCI/SRAM
TID>100KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU LETTH >15 MeV·cm2·mg-1
|
| 65nm
|
IP: SerDes/PLL/LVDS/SRAM/PCI IO/DDR IO/LVPECL
TID>300KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU Rate<10-10 error/bit-day
|
| 28nm
|
IP: SerDes/PLL/SRAM
TID>300KRad (Si) /SEL LETTH>90 MeV·cm2·mg-1 /SEU Rate<10-10 error/bit-day
|
